Journals:

1. F. Akyildiz, M. Ghovanloo, U. Guler, T. Ozkaya-Ahmadov, P. Rather, A. F. Sarioglu, and B. D. Unluturk, “PANACEA: An Internet of Bio-NanoThings Application for Early Detection and Mitigation of Infectious Diseases”,
2. U. Guler, and M. Ghovanloo, “Power Management in Wireless Power-Sipping Devices: A Survey,” IEEE Circuits and Systems Magazine, Vol. 17, No. 4, pp. 64-82, Nov. 2017.
3. U. Guler, A. E. Pusane, and G. Dundar “Design of Efficient CMOS Ring Oscillator Based Random Number Generator,” International Journal of Electronics, Vol. 104, No.9, pp. 1465 – 1482, April 2017.
4. U. Guler, and G. Dundar “Modelling CMOS Ring Oscillator Performance for Randomness Source,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 61, No. 3, pp. 712 – 724, March 2014.
5. U. Guler, and S. Ergun, “A High Speed, Fully Digital IC Random Number Generator,” International Journal of Electronics and Communications (AEU), Vol. 66, No. 2, pp. 143 – 149, February 2012.
6. S. Ergun, U. Guler, and K. Asada,  “IC truly random number generators based on regular and chaotic sampling of chaotic waveforms,” IEICE Transactions on Nonlinear Theory and Its Applications, Vol. 2, No. 2,  pp. 246 – 261, April 2011.
7. S. Ergun, U. Guler, and K. Asada,  “A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 1, pp. 180 – 190, January 2011.
8. U. Ekinciel, H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada, “A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells,” IEICE Transaction on Information and Systems, Vol. E88-D, No. 6, pp. 1159-1167, June 2005.

Conferences:

1. A. Munge, V. Sankar, M.S.E. Sendi, M. Ghovanloo, and U. Guler “A Bio-Impedance Measurement IC for Neural Interface Applications,” Proceedings of 2018 IEEE Biomedical Circuits and Systems Conference, BIOCAS 2018, pp. , October 2018.
2. U. Guler, M.S.E Sendi, and M. Ghovanloo, “A Dual-Mode Passive Rectifier for Wide-Range Input Power Flow”, Proceedings of 2017 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017, pp. 1376 – 1379, August 2017.
3. U. Guler, A. E. Pusane, and G. Dündar, “Investigating Flicker Noise Effect on Randomness of CMOS Ring Oscillator based True Random Number Generators,” Proceedings of International Conference on Information Science, Electronics and Electrical Engineering, ISEEE 2014, pp.845-849, May 2014.
4. U. Guler, “A New RNG Evaluation Method,” 14th International Common Criteria Conference, ICCC 2013, September 2013.
5. U. Guler, and G. Dundar, “Modelling Phase Noise and Jitter in Subthreshold Region and Assessing the Randomness Performance of CMOS Ring Oscillators,” Proceedings of International Conference on Synthesis, Modelling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012, pp. 257 – 260, September 2012.
6. U. Guler, and G. Dundar “Maximizing Randomness in Ring Oscillators for Security Applications,” Proceedings of 2011 20th IEEE European Conference on Circuit Theory and Design, ECCTD 2011, pp. 117 – 120, August 2011.
7. U. Guler, S. Ergun, and G. Dundar “A Digital IC Random Number Generator With Logic Gates Only,” Proceedings of 2010 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, pp. 239 – 242, December 2010.
8. U. Guler, and S. Ergun, “Monolithic Implementation of a Double-Scroll Chaotic Attractor and Application to Random Number Generation,” Proceedings of 2010 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, pp. 1037 – 1040, December 2010.
9. U. Guler, and S. Ergun, “A high speed IC Random Number Generator based on phase noise in ring oscillators,” Proceedings of 2010 IEEE International Symposium on Circuits and Systems, ISCAS 2010, pp. 425 – 428, May 2010.
10. U. Guler, A. Bozkurt, “A Low-Noise Front-End Circuit for 2D cMUT Arrays,” Proceedings of the 2006 IEEE Ultrasonics Symposium, US 2006, Sept. 2006
11. U. Ekinciel, M. Ikeda, and K. Asada, “An SRAM-based Field Programmable Logic Array Design,” IEICE Society Conference 2004, Sept. 2004.
12. U. Ekinciel, H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada, “Constraint Driven Dual-rail PLA Module Generator with Embedded 2-Input Logic Cells,” 12th IEEE Mediterranean Electrotechnical Conference, MELECON 2004 pp. 189 – 192, May 2004.
13. U. Ekinciel, H. Yamaoka, M. Ikeda, and K. Asada, “Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells,” IEICE Technical Report, VLD2003, March 2003.
14. U. Ekinciel, H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada, “A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells,” IEICE Society Conference 2002, Sept. 2002.